The present invention relates to a semiconductor device having a plurality of wiring layers, and more specifically relates to a wiring structure of a semiconductor device.
Wiring resistance of a source wiring for supplying electric power to a circuit element in a semiconductor device must be set sufficiently small. Otherwise, severe voltage drop occurs when a current flows in the source wiring at initiation of the operation of the circuit element, inviting increase in operation delay and erroneous operation of the circuit element. In this connection, design of source wirings in semiconductor devices becomes a key in association with recent increase in scale and integration of semiconductor devices.
Especially, semiconductor devices that consume much power encounter remarkable voltage drop in the source wirings, and therefore, source wiring structures capable of stably supplying power to the circuit elements with less voltage drop are demanded.
In semiconductor devices having source wiring structures capable of stably supplying power, there is a device in which source wirings having widths corresponding to a total sum of power necessary for respective circuit elements on a semiconductor chip are arranged in mesh (for example, see Japanese Patent Application Laid Open Publication No. 5-335484A).
FIG. 8 is a plan view showing a source wiring structure of a conventional semiconductor device. Also, FIG. 9 is a view stereoscopically showing the positional relationship of each constitutional element shown in FIG. 8.
As shown in the drawings, the conventional semiconductor substrate 600 includes: a mesh source wiring 610, which is composed of first source wirings 620 formed on a wiring layer, second source wirings 630 formed on another wiring layer, and contacts 640 for mesh source wiring; cell source wirings 650 formed on a layer lower than the layers where the mesh source wiring 610 is formed; contacts 660 for cell source wiring; and circuit elements 670.
The widths and the numbers of the first source wirings 620 and the second source wirings 630 correspond to a total sum of power necessary for the circuit elements 670.
The contacts 640 for mesh source wiring connect the first source wirings 620 and the second source wirings 630.
The contacts 660 for cell source wiring connect the second source wirings 630 and the cell source wirings 650 with each other.
In the semiconductor device thus structured, when the mesh source wiring 610 is connected to a power source (or grounded) by means of a power supply terminal (not shown), the power is supplied stably to the circuit elements 670 through the contacts 660 for cell source wiring and the cell source wirings 650.
However, the above conventional semiconductor device involves the following problems.
In general, the mesh source wiring 610 occupies the uppermost wiring layer and the wiring layer just below it while the cell source wirings 650 lie on the lowermost wiring layer. Accordingly, a plurality of wiring layers lie between the wiring layer where the second source wirings 630 are formed and the wiring layer where the cell source wirings 650 are formed.
In this connection, for connecting parts where the mesh source wiring 610 and the cell source wirings 650 intersect with each other, it is necessary to form many contacts 660 for cell source wiring which pass through a plurality of wiring layers. Namely, the contacts 660 for cell source wiring consume wiring resources (region required for wiring) in a plurality of wiring layers, which in turn inhibits efficient wiring of singal wirings.
Particularly, in association with increase in number of wiring layers for high integration of semiconductor devices, the number of wiring layers between the mesh source wiring 610 and the cell source wirings 650 increases, so that the influence that the contacts 660 for cell source wiring consume the wiring resources grows severely.
Further, in association with miniaturization of wirings in progress of semiconductor device manufacturing technology, wiring resistance per unit length increases. However, mere widening the wiring width of the mesh source wiring 610 and the cell source wirings 650 in the generation of, for example, about 0.13 μm process attains insufficient lowering of the wiring resistance of the source wirings. In this way, it is difficult to suppress voltage drop of the source voltage to be supplied to the circuit elements 670.
In miniaturized wirings, the upper limit of the wiring width is restricted for increasing a manufacturing yield, so that voltage drop of the source voltage is difficult to be sufficiently suppressed even if the widths of all source wirings are set large as far as possible.
The upper two wiring layers that the mesh source wiring 610 occupies generally have wiring resistances per unit length lower than the other wiring layers, and therefore, it is useful for arranging signal wirings having high frequencies. While, as the wiring intervals of the mesh source wiring 610 becomes narrower for lowering the wiring resistance of the source wirings, the wiring resources for signal wiring in the upper two wiring layers are consumed more. In consequence, the signal wirings having high frequencies have to be formed on other wiring layers. This degrades the timing of the signal wirings and necessitates increase in area of the semiconductor device for supplementing the short of the wiring resources.
Furthermore, the timing degradation involves many design steps for countermeasures thereto, inviting increase in design period. Also, the increase in area of the semiconductor device invites voltage drop of the source voltage caused due to increase in lengthy routed source wirings and increases in manufacturing cost because of a lowered yield of the semiconductor device.